/**
 给逻辑分析仪时钟
**/
module prode_clk
#(
    parameter CNT_MAX=100
)
(
   input  clk,
   input  rst_n,
   output reg dout
);

reg[15:0] cnt=0;
wire cnt_add;
wire cnt_end;
assign cnt_add = 1;
assign cnt_end = cnt_add && cnt== CNT_MAX-1;


always @(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		cnt <= 0;
	end
	else if(cnt_add)begin
		if(cnt_end)
			cnt <= 0;
		else
			cnt <= cnt + 1;
	end
end


always @(posedge clk or negedge rst_n)begin
    if(rst_n==1'b0)
       dout<=0;
    else if(cnt_end)
       dout<=!dout;
end

endmodule
